FPGA Verilog simulation using GTKWave on the iCE40-feather [waynejohnson.net]

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FPGA Verilog simulation using GTKWave on the iCE-feather

One of the nice things about working with FPGAs and Verilog is the array of open source tools and development boards that are available.

For this article I'll be using the iCE-feather development board by Josh Johnson which is based on the ICEBreaker board, but the simulation set up should be the same for many boards.

If you are using an iCE-feather, you can follow the set up instructions to get the icestorm toolchain installed, and get drivers working for this FTDI based board.

Our aim is to take a verilog file, a testbench and simulate it using Icarus Verilog / GTKWave.

Setting up a project

We'll start with a simple standard blinker in one file.

Create a folder called:

simple-blink

Create a verilog file inside the folder and call it blink.v:

`default_nettype none
 
module top #(parameter integer DELAY = 2500000) (
    input wire clk,
    output wire nLED_GRN
    );
 
  reg [31:0] r_MAX = DELAY;
  reg [31:0] r_COUNT = 0;
 
  reg r_led = 0;
 
  always @ (posedge clk)
  begin
    if (r_COUNT < r_MAX)
      begin
        r_COUNT <= r_COUNT + 1;
      end
    else
      begin
        r_COUNT <= 0;
        r_led <= !r_led;
      end
  end
 
  assign nLED_GRN = r_led;
 
endmodule

Nice and simple, blink the red LED on the iCE-feather board after several thousand clock cycles.

Now a testbench file, create a blink_tb.v file in our project folder:

`timescale 1ns/1ns
`include "blink.v"
 
module blink_tb;
 
  reg tClk = 1'b0;
  wire tLed;
 
  top #(
    .DELAY(10)
  ) UUT
  (
    .clk(tClk),
    .nLED_GRN(tLed)
  );
 
  always #2 tClk <= !tClk;
 
  // Dump wave
	initial begin
		$dumpfile("blink_tb.lxt");
		$dumpvars(0,blink_tb);
	end
 
  initial
    begin
      #100;
      $finish;
    end
 
endmodule

I'll explain a couple of things from the testbench. Firstly, an ns timescale is being used. So each time unit is a nanosecond. This will keep the timescale nice and compressed to view in the simulation. In the real module, the timescale has too much data to comfortably view.

There is a dump file generated using the testbench. Icarus Verilog / GTKWave uses these files for its simulation.

Now to download and install Icarus Verilog / GTKWave from: http://bleyer.org/icarus

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