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open_source_on_goboard [2021/02/22 12:32] sausage created |
open_source_on_goboard [2021/02/23 11:26] (current) sausage [Extra Notes] |
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We are only interested in the clock-in and the pin that goes to the second LED (I picked that at random). That's all that will be in the constraints file. | We are only interested in the clock-in and the pin that goes to the second LED (I picked that at random). That's all that will be in the constraints file. | ||
+ | There is no harm in supplying the full constraints file if you prefer. You'll just see some "Warning: unmatched constraint" messages during the place and route step. | ||
===== The FPGA Code ===== | ===== The FPGA Code ===== | ||
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For ''yosys'' you can script the various commands that we entered earlier to help partially automate your workflow. | For ''yosys'' you can script the various commands that we entered earlier to help partially automate your workflow. | ||
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+ | For the constaints file, you can supply the entire set of constraints, but you will receive harmless warnings. If you would like to supress the warnings, add the ''-nowarn'' flag to each entry in the PCF file like this: | ||
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+ | set_io -nowarn o_LED_2 57 | ||
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===== Troubleshooting ===== | ===== Troubleshooting ===== |