verilog_wire_and_reg
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- dokuwiki-128.png
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![[root]](/doku.php/verilog_wire_and_reg?ns=&tab_files=files&do=media&tab_details=view&image=wiki%3Agtkwave-with-signals.png){kind=link}
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- Date:
- 2021/02/02 01:24
- Filename:
- gtkwave-with-signals.png
- Format:
- PNG
- Size:
- 11KB
- Width:
- 870
- Height:
- 568
- References for:
- FPGA Verilog simulation using GTKWave on the iCE40-feather
verilog_wire_and_reg.txt · Last modified: 2021/03/04 10:41 by sausage
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