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pic16f1455_oscillators [2019/10/04 18:59] 60.240.96.191 created |
pic16f1455_oscillators [2020/10/02 20:27] 127.0.0.1 external edit |
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Page 73 of the [[http://ww1.microchip.com/downloads/en/DeviceDoc/40001639B.pdf|datasheet]] tells us that 500kHz is the "default upon Reset". So that is the default power-on frequency of the PIC16F1455. | Page 73 of the [[http://ww1.microchip.com/downloads/en/DeviceDoc/40001639B.pdf|datasheet]] tells us that 500kHz is the "default upon Reset". So that is the default power-on frequency of the PIC16F1455. | ||
- | If you need a basic breadboard wiring diagram for the PIC16F1455, you can check the previous article. | + | If you need a basic breadboard wiring diagram for the PIC16F1455, you can check the [[pic16f1455|previous article]]. |
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The on and off will be accurately changing every second, thanks to ensuring that ''_XTAL_FREQ'' matches the frequency chosen with the ''IRCF'' bits in the ''OSCCON'' register. | The on and off will be accurately changing every second, thanks to ensuring that ''_XTAL_FREQ'' matches the frequency chosen with the ''IRCF'' bits in the ''OSCCON'' register. | ||
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+ | If you're observant, you may notice that the blinking interval is not exactly one second. I'll cover why shortly. | ||
===== Using PLL to achieve 24MHz ===== | ===== Using PLL to achieve 24MHz ===== | ||
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The datasheet does not list what the default for clock division is when resetting a PIC. However, the default in the configuration bits is shown as: ''CLKDIV6'' (using the MPLAB X IDE). Which means to divide the CPU clock by six. Or... make the CPU a sixth the normal speed. | The datasheet does not list what the default for clock division is when resetting a PIC. However, the default in the configuration bits is shown as: ''CLKDIV6'' (using the MPLAB X IDE). Which means to divide the CPU clock by six. Or... make the CPU a sixth the normal speed. | ||
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+ | And this is why the interval was not quite correct when we were setting the 62.5kHz frequency in the previous section. It was because there was some CLKDIV dividing set. | ||
===== Low Frequency Internal Oscillator (LFINTOSC) ===== | ===== Low Frequency Internal Oscillator (LFINTOSC) ===== | ||
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#define _XTAL_FREQ 17664000UL //17.664MHz | #define _XTAL_FREQ 17664000UL //17.664MHz | ||
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+ | Ensure the PLL is off to ensure good timing: | ||
+ | |||
+ | #pragma config PLLEN = 0 //Turn off PLL | ||
And finally, the only ''OSCCON'' register setting you need is: | And finally, the only ''OSCCON'' register setting you need is: |